(3) When address 0 (D1, D0) = (1, 0)
100 pF
RESET VD LATCH SCLK SDATA CLK
7
8
4
5
6
14
VDD 47
LGND 13
Serial control block
CLKB COSC OSC
15
9
10
100 pF
OSC OSC
VM12 18
OUT1A 17
OUT1B 19
16
PGND12
20
VM12 22
OUT2A 21
M
OUT2B 23
PGND 24
Ch1
H-bridge
Ch2
H-bridge
VM5 27
25
PGND5
29
Ch5
H-bridge
26
28
OUT5A OUT5B
30
RSEN5
31
RSEN6
39 VM3
Ch3
H-bridge
38 OUT3A
40 OUT3B
37
PGND34
41
43 VM4
Ch4
H-bridge
42 OUT4A
M
44 OUT4B
45 PGND34
Ch6
H-bridge
33
35
OUT6A OUT6B
34 VM6
32
PGND6
36
M
M
(4) When address 0 (D1, D0) = (1, 1)
100 pF
RESET VD LATCH SCLK SDATA CLK
7
8
4
5
6
14
VDD 47
LGND 13
Serial control block
CLKB COSC OSC
15
9
10
100 pF
OSC OSC
VM12 18
OUT1A 17
OUT1B 19
16
PGND12
20
VM12 22
OUT2A 21
M
OUT2B 23
PGND 24
Ch1
H-bridge
Ch2
H-bridge
VM5 27
25
PGND5
29
Ch5
H-bridge
26 28
OUT5A OUT5B
30
RSEN5
1 kΩ
39 VM3
Ch3
H-bridge
38 OUT3A
M
40 OUT3B
37
PGND34
41
43 VM4
Ch4
H-bridge
42 OUT4A
M
44 OUT4B
45 PGND34
31
RSEN6
Ch6
H-bridge
33
35
OUT6A OUT6B
34 VM6
32
PGND6
36
1 kΩ
µPD168112
Data Sheet S15866EJ1V0DS
7