UPD6376CX 查看數據表（PDF） - NEC => Renesas Technology

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UPD6376CX

AUDIO 2-CHANNEL 16-BIT D/A CONVERTER

NEC => Renesas Technology 

µPD6376

2.2 Supplying Clock to CLK only during Sample Data Interval

The analog outputs of the L.OUT and R.OUT pins are updated after the input of 4.5 clocks following data input.

(See 4. ELECTRICAL CHARACTERISTICS, Timing Charts 1 and 2.)

2.2.1 Inputting serial data (Pin 1 Low or Open)

Place the LRCK reverse timing between the falling edge of CLK at LSB input completion (Point A in Figure 2-3)

and the next MSB input start time (Point B in Figure 2-3) (so as to include Points A and B).

Figure 2-3 Timing Chart of Serial Data Input

A

CLK

LSB

SI 16

B

A

1-sample data interval

MSB

LSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

B

MSB

1234

LRCK

LRCK reverse interval

LRCK reverse interval

2.2.2 Inputting parallel data (Pin 1 High)

Place the WDCK falling edge timing between the falling edge of CLK at LSB input completion (Point A in Figure

2-4) and the next MSB input start time (Point B in Figure 2-4) (so as to include Points A and B).

Place the WDCK rising edge timing between the third falling edge of CLK from MSB input completion (Point C in

Figure 2-4) and the falling edge of CLK upon LSB input start (Point D in Figure 2-4) (so as to include Points C and

D).

Figure 2-4 Timing Chart of Parallel Data Input

A

B

C

DA

B

CLK

LSB

LSI 16

LSB

RSI 16

MSB

LSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MSB

LSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MSB

12

MSB

12

WDCK

WDCK falling

edge interval

WDCK rising edge interval

WDCK falling

edge interval

7

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