CLM7660 查看數據表（PDF） - Calogic, LLC

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CLM7660

DC-to-DC Voltage Converter

Calogic, LLC 

CORPORATION

CLM7660

CIRCUIT DESCRIPTION

The CLM7660 is an excellent voltage doubler, the device has

all the characteristic with the exception of two inexpensive

10µF polarized electrolytic external capacitors. Figure 3

demonstrates the most effective means of using the device as

a voltage doubler. Capacitor C1 is charged to a voltage, V+,

for the half cycle when switches S1 and S3 are closed. (Note

Switches S2 and S4 are open during this half cycle.) During

the second half of the operation, switches S2 and S4 are

closed, with S1 and S3 open, thereby shifting capacitor C1

negatively by V+ volts. Charge is then transferred from C1 to

C2, such that voltage on C2 is exactly V+, asumming ideal

switches and no load on C2.

The four switches in Figure 3 are MOS power switches, S1 is

a P-Channel device, S2, S3 and S4 are N-Channel devices.

The major challenge with this approach while integrating the

switches, the substrates of S3 and S4 must always remain

reversed-biased with respect to their sources, but not so

much as to degrade their ON-resistances. In addition, at

circuit start-up, and under short circuit conditions (VOUT=V+),

the output voltage must be sensed and the substrate bias

adjusted accordingly. Failure to accomplish this will result in

high power losses and probable device latch-up.

The above problem is eliminated in the CLM7660 by a logic

network which senses the output voltage (VOUT) together with

the level translators, and switches the substrates of S3 and S4

to the correct level to maintain necessary reverse bias.

The voltage regulator portion of the CLM7660 is an integral

part of the anti-latch-up circuitry. Its inherent voltage drop can

degrade operation at low voltages. To improve low-voltage

operation, the LV pin should be connected to GND, disabling

the regulator. For supply voltages greater than 3.5V, the LV

terminal must be left open to ensure latch-up proof operation

and prevent device damage.

THEORETICAL POWER EFFICIENCY CONSIDERATIONS

In theory, a voltage multiplier can approach 100% efficiency if

certain conditions are met:

1. The drive circuitry consumes minimal power.

2. The output switches have extremely low ON-resistance and

virtually no offset.

3. The impedances of the pump and reservoir capacitors are

negligible at the pump frequency.

When larger values of C1 and C2 are used, the CLM7660

approaches the above conditions for negative voltage

multiplication. Energy is lost only if the transfer of the charge

between capacitors if a change in voltage occurs. The energy

lost is defined by:

E=1/2C1 (V12-V22)

During the pump and transfer cycles V1 and V2 are the

voltages on C1. If the impedances of C1 and C2 are high at

the pump frequency (see Figure 3), compared to the value of

RL, there will be a substantial difference in voltages V1 and

V2. The most optimum selection would be to make C2 as

large as possible to eliminate output voltage ripple, and to

utilize a large value for C1 to achieve maximum efficiency of

operation.

OPERATIONAL RULES:

Never exceed maximum supply voltages.

Never connect LV terminal to GND for supply voltages over

3.5V.

Never short circuit the output to V+ supply voltages above

5.5V for extended periods; however, transient conditions

including start-up are acceptable.

For polarized capacitors, the + terminal of C1 must be

connected to pin 2 of the CLM7660 and the + terminal to of C2

must be connected to GND.

For high-voltage, elevated temperature applications add a

diode DX (reference Figure 1). The 1N914 diode is an

appropriate choice.

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-3025

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