V53C808H35 查看數據表（PDF） - Mosel Vitelic Corporation

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V53C808H35

HIGH PERFORMANCE 1M x 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH

Mosel Vitelic Corporation  

MOSEL VITELIC

Extended Data Output Page Mode

EDO Page operation permits all 1024 columns

within a selected row of the device to be randomly

accessed at a high data rate. Maintaining RAS low

while performing successive CAS cycles retains the

row address internally and eliminates the need to

reapply it for each cycle. The column address buffer

acts as a transparent or flow-through latch while

CAS is high. Thus, access begins from the

occurrence of a valid column address rather than

from the falling edge of CAS, eliminating tASC and tT

from the critical timing path. CAS latches the

address into the column address buffer. During

EDO operation, Read, Write, Read-Modify-Write or

Read-Write-Read cycles are possible at random

addresses within a row. Following the initial entry

cycle into Hyper Page Mode, access is tCAA or tCAP

controlled. If the column address is valid prior to the

rising edge of CAS, the access time is referenced to

the CAS rising edge and is specified by tCAP. If the

column address is valid after the rising CAS edge,

access is timed from the occurrence of a valid

address and is specified by tCAA. In both cases, the

falling edge of CAS latches the address and

enables the output.

EDO provides a sustained data rate of 72 MHz for

applications that require high bandwidth such as bit-

mapped graphics or high-speed signal processing.

The following equation can be used to calculate the

maximum data rate:

Data Rate = t--R----C-----+-----11---00----22---43-----´-----t--P---C--

V53C808H

Self Refresh (Optional)

Self Refresh mode provides internal refresh con-

trol signals to the DRAM during extended periods of

inactivity. Device operation in this mode provides

additional power savings and design ease by elimi-

nation of external refresh control signals. Self Re-

fresh mode is initialed with a CAS before RAS

(CBR) Refresh cycle, holding both RAS low (tRASS)

and CAS low (tCHD) for a specified period. Both of

these parameters are specified with minimum val-

ues to guarantee entry into Self Refresh operation.

Once the device has been placed in to Self Refresh

mode the CAS clock is no longer required to main-

tain Self Refresh operation.

The Self Refresh mode is terminated by returning

the RAS clock to a high level for a specified (tRPS)

minimum time. After termination of the Self Refresh

cycle normal accesses to the device may be initiat-

ed immediately, poviding that subsequest refresh

cycles utilize the CAS before RAS (CBR) mode of

operation.

Data Output Operation

The V53C808H Input/Output is controlled by OE,

CAS, WE and RAS. A RAS low transition enables

the transfer of data to and from the selected row

address in the Memory Array. A RAS high transition

disables data transfer and latches the output data if

the output is enabled. After a memory cycle is

initiated with a RAS low transition, a CAS low

transition or CAS low level enables the internal I/O

path. A CAS high transition or a CAS high level

disables the I/O path and the output driver if it is

enabled. A CAS low transition while RAS is high has

no effect on the I/O data path or on the output

drivers. The output drivers, when otherwise

enabled, can be disabled by holding OE high. The

OE signal has no effect on any data stored in the

output latches. A WE low level can also disable the

output drivers when CAS is low. During a Write

cycle, if WE goes low at a time in relationship to

CAS that would normally cause the outputs to be

active, it is necessary to use OE to disable the

output drivers prior to the WE low transition to allow

Data In Setup Time (tDS) to be satisfied.

V53C808H Rev. 1.5 April 1998

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