W167B 查看數據表（PDF） - Cypress Semiconductor
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W167B Datasheet PDF : 18 Pages
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PRELIMINARY
W167B
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 0–6. Table 5 details additional frequency selections that
are available through the serial data interface. Table 6 details
the select functions for Byte 0, bits 1 and 0.
Table 4. Data Bytes 0–6 Serial Configuration Map
Affected Pin
Bit(s) Pin No. Pin Name
Control Function
Data Byte 0
7
--
--
SEL133/100#
6
--
--
SEL2
5
--
--
SEL1
4
--
--
SEL0
3
--
--
Frequency Table Selection
2
--
1-0
--
Data Byte 1
7
27
6
28
5
--
4
42
3
--
2
39
1
36
0
35
Data Byte 2
7
16
6
15
5
13
4
12
3
11
2
10
1
8
0
7
Data Byte 3
7
--
6
23
5
22
4
21
3
--
2
--
1
19
0
18
--
(Reserved)
--
Functional control
48MHz
24/48MHz
--
CPUdiv2
--
CPU2
CPU1
CPU0
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
3V66_2
3V66_1
3V66_0
--
--
PCI9
PCI8
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Bit Control
0
1
Default
Refer to Table 5
0
Refer to Table 5
0
Refer to Table 5
0
Refer to Table 5
0
Controlled by exter- Controlled by BYTE0
0
nal pin (per Table 1)
(per Table 5)
--
--
0
Refer to Table 6
00
Low
Active
1
Low
Active
1
--
--
0
Low
Active
1
--
--
0
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
Low
Active
1
--
--
0
Low
Active
1
Low
Active
1
Low
Active
1
--
--
0
--
--
0
Low
Active
1
Low
Active
1
7
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