W83194BR-SD 查看數據表（PDF） - Winbond

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W83194BR-SD

Winbond Clock Generator For INTEL P4 Springdale Series Chipset

Winbond 

W83194BR-SD/W83194BG-SD

CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET

7. I2C CONTROL AND STATUS REGISTERS

(The register No. Is increased by 1 if use byte data read/write protocol)

7.1 Register 0: Frequency Select (Default =10H)

BIT

NAME

PWD

DESCRIPTION

7

SSEL [4]

0

6

SSEL [3]

5

SSEL [2]

0

0 Software frequency table selection through I2C

4

SSEL [1]

1

3

SSEL [0]

0

Enable software table selection FS [4:0].

2

EN_SSEL

0 0 = Hardware table setting (Jump mode).

1 = Software table setting through Bit7~3. (Jump less mode)

Enable spread spectrum mode under clock output.

1

SPSPEN

0 0 = Spread Spectrum mode disable

1 = Spread Spectrum mode enable

After watchdog timeout

0

EN_SAFE_FRE

Q

0

0 = Reload the hardware FS [4:0] latched pins setting.

1 = Reload the desirable frequency table selection defined at Reg-5

Bit 4~0.

7.2 Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default = E3H)

BIT

NAME

PWD

DESCRIPTION

SRCCLKT

7

SRCCLKC

1 Pin 37,36 SRCCLK T/C output control

CPUCLKT1

6

CPUCLKC1

1 Pin 43,42 CPUCLKT1/C1 output control

CPUCLKT0

5

CPUCLKC0

1 Pin 40,39 CPUCLKT0/C0 output control

4

FS4

X Power on latched value of FS4 (9) pin, Default 0 (Read only)

3

FS3

X Power on latched value of FS3 (22) pin. Default 0 (Read only)

2

FS2

X Power on latched value of FS2 (8) pin. Default 0 (Read only)

1

FS1

X Power on latched value of FS1 (1) pin. Default 1 (Read only)

0

FS0

X Power on latched value of FS0 (2) pin. Default 1 (Read only)

Publication Release Date: March, 22, 2006

-7-

Revision 1.2

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