W83195BG-118 查看數據表（PDF） - Winbond

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W83195BG-118

Clock Generator

Winbond 

W83195BR-118/W83195BG-118

STEPLESS FOR INTEL 915/945 CHIPSETS

7.11 Register 10: Reserved (Default: 3Bh)

BIT

NAME

PWD

DESCRIPTION

7 SRC_SPSPEN 0 Enable SRC spread spectrum feature

6

Reserved

1: Enable

0: Disable

0 Reserved

5

Reserved

1 Reserved

4

Reserved

1 Reserved

3

Reserved

1 Reserved

2

Reserved

0 Reserved

1

Reserved

1 Reserved

0

Reserved

1 Reserved

TYPE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

7.12 Register 11: Spread Spectrum Programming (Default: 0Eh)

BIT

NAME PWD

DESCRIPTION

7

SP_UP [3] 0 Spread Spectrum Up Counter bit 3 ~ bit 0.

6 SP_UP [2] 0

5 SP_UP [1] 0

4 SP_UP [0] 0

3 SP_DOWN [3] 1 Spread Spectrum Down Counter bit 3 ~ bit 0

2 SP_DOWN [2] 1 2’s complement representation.

1 SP_DOWN [1] 1 Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000

0 SP_DOWN [0] 0

TYPE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

7.13 Register 12: Divisor Control (Default: 08h)

BIT

NAME

PWD

DESCRIPTION

7

Reserved

0 Reserved

6

KVAL6

X Define the PCI divider ratio

5

KVAL5

X Table-2 integrate the all divider configuration

4

KVAL4

X Define the PCIE divider ratio

3

KVAL3

X Refer to Table-2

2

KVAL2

X Define the CPU divider ratio

1

KVAL1

X Refer to Table-2

0

KVAL0

X

- 12 -

TYPE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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