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W83195BG-118 查看數據表(PDF) - Winbond

零件编号
产品描述 (功能)
比赛名单
W83195BG-118
Winbond
Winbond Winbond
W83195BG-118 Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
W83195BR-118/W83195BG-118
STEPLESS FOR INTEL 915/945 CHIPSETS
5.1 Crystal I/O
PIN
PIN NAME
48 XIN
47 XOUT
TYPE
DESCRIPTION
IN
OUT
Crystal input with internal loading capacitors (18pF) and
feedback resistors.
Crystal output at 14.318MHz nominally with internal loading
capacitors (18pF).
5.2 CPU and PCIE, PCI, Clock Outputs
PIN
PIN NAME
43,42,40,39 CPUT [0:1]
CPUC [0:1]
17,18,21,22 PCIET [0:4]
,23,24,31,3 PCIEC [0:4]
0,33,32
7
PCI_F0
8
PCI_F1
&FS0
9
PCI_F2
*FS1
53,54,55,2, PCI [0:5]
3,4
TYPE
DESCRIPTION
OUT
OUT
Low skew (< 125ps) 0.7V Current mode differential clock
outputs for host frequencies of CPU
Low skew (<125ps) 0.7V Current mode differential clock
outputs for PCI-Express
OUT 3.3V free running PCI clock output.
OUT 3.3V free running PCI clock output.
INtd120k Latched input for FS0 at initial power up for H/W selecting
the output frequency. Latched voltage level refers to Vil_FS
and Vih_FS voltage level. This is internal 120K pull down.
OUT 3.3V free running PCI clock output.
INtp120k Latched input for FS1 at initial power up for H/W selecting
the output frequency. Latched voltage level refers to Vil_FS
and Vih_FS voltage level. This is internal 120K pull up.
OUT Low skew (< 500ps) 3.3V PCI clock outputs
5.3 Fixed Frequency Outputs
PIN
PIN NAME
REF0
51
&FS2
50 REF1
11 24_48MHz
&SEL24_48#
TYPE
DESCRIPTION
OUT 3.3V REF 14.318Mhz clock output.
INtd120k
OUT
OUT
INtd120k
Latched input for FS2 at initial power up for H/W selecting
the output frequency, Latched voltage level refers to Vil_FS
and Vih_FS voltage level. This is internal 120K pull down.
3.3V REF 14.318Mhz clock output.
24MHz or 48MHz (default) clock output, In power on reset
period, it is a hardware-latched pin, and it can be R/W by
I2C control after power on reset period. Select by register 5
bit 7.
Latched input for 24MHz or 48MHz select pin. This is
internal 120K pull down default 48MHz. In power on reset
period, it is a hardware-latched pin, and it can be R/W by
I2C control after power on reset period. Select by register 5
bit 7.
-4-

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