W83176R-733/W83176G-733
DUAL BANK DDR BUFFER FOR VIA CHIPSET
6. POWER PINS
PIN
2,9,15,24,27,34,40,47
1,10,16,23,28,33,39,48
PIN NAME
GND
VDD2.5
DESCRIPTION
Ground
Power Supply 2.5V
7. I2C CONTROL AND STATUS REGISTERS
7.1 Register 0 ~ Register 5 RESERVED
7.2 Register 6: Output Control (1 = Enable, 0 = Disable) (Default: FFh)
BIT
PIN NO
7
Reserved
6
17
5
36,35
4
38,37
3
21,22
2
20,19
1
13,14
0
11,12
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
Reserved
FB_OUTA output control
DDRA_T5/C5 output control
DDRA_T4/C4 output control
DDRA_T3/C3 output control
DDRA_T2/C2 output control
DDRA_T1/C1 output control
DDRA_T0/C0 output control
7.3 Register 7: Output Control (1 = Enable, 0 = Disable) (Default: FFh)
Bit
Pin No
PWD
Description
7
Reserved
1
Reserved
6
3
1
FB_OUTB output control
5
30,29
1
DDRB_T5/C5 output control
4
32,31
1
DDRB_T4/C4 output control
3
42,41
1
DDRB_T3/C3 output control
2
44,43
1
DDRB_T2/C2 output control
1
7,8
1
DDRB_T1/C1 output control
0
5,6
1
DDRB_T0/C0 output control
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