STFLSTUDIO2/KIT 查看數據表（PDF） - STMicroelectronics
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STFLSTUDIO2/KIT Datasheet PDF : 28 Pages
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W.A.R.P.2.0
Table 1. Pin Description
Pin Assignment
11,26,31,40,48,57
1,10,25,30,39,47,56
19
12
13
15
65
Name
VDD
VSS
TEST
MCLK
PRESET
AUTO
SIS0
64
SIS1
63
SIS2
67
I0
68
I1
2
I2
3
I3
4
I4
5
I5
6
I6
7
I7
14
OF L
18
RD
16
LASTIN
17
OE
66
WAIT
24
READY
21
ENDOFL
23
BUSY
20
DS
22
ERR
33
OC0
32
OC1
55
O0
54
O1
53
O2
52
O3
51
O4
50
O5
49
O6
38
O7
37
O8
36
O9
35
O10
34
O11
Pins Type
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Fun ction
Power Supply
Ground
Testing (It must be connected to VSS)
Master Clock (up to 40 MHz)
Preset
Auto/Manual-Boot
Auto-Boot Speed (Ext. Memory Support AccessTime) /
Input Selection bit 0
Auto-Boot Speed (Ext. Memory Support Access Time) /
Input Selection bit 1
Auto-Boot Speed (Ext. Memory Support Access Time) /
Input Selection bit 2
Data Input bit 0
Data Input bit 1
Data Input bit 2
Data Input bit 3
Data Input bit 4
Data Input bit 5
Data Input bit 6
Data Input bit 7
Off-Line/On-Line Switch
Handshaking Read Ready
Last Input (Start Elaboration) bit
Output Enable/3-STATE bit
Temporary Output Processing Stop
Handshaking Output Signal
Offline Phase (external memory downloading) End
Elaboration Phase Indicator
Data Strobe (Output Ready Signal)
Error Flag
Output Identifier bit 0
Output Identifier bit 1
External Memory Address/Defuzzified Output bit 0
External Memory Address/Defuzzified Output bit 1
External Memory Address/Defuzzified Output bit 2
External Memory Address/Defuzzified Output bit 3
External Memory Address/Defuzzified Output bit 4
External Memory Address/Defuzzified Output bit 5
External Memory Address/Defuzzified Output bit 6
External Memory Address/Defuzzified Output bit 7
External Memory Address bit 8 /
Next Input Progressive Number bit 0
External Memory Address bit 9 /
Next Input Progressive Number bit 1
External Memory Address bit 10 /
Next Input Progressive Number bit 2
External Memory Address bit 11 /
Start Conversion for the external A/D
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