datasheetbank_Logo
数据手册搜索引擎和 Datasheet免费下载 PDF

W9864G6IH 查看數據表(PDF) - Winbond

零件编号
产品描述 (功能)
比赛名单
W9864G6IH Datasheet PDF : 43 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
W9864G6IH
1. GENERAL DESCRIPTION
W9864G6IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words × 4 banks × 16 bits. W9864G6IH delivers a data bandwidth of up to 200M words per second.
For different application, W9864G6IH is sorted into the following speed grades: -5, -6, -7/-7S. The -5
parts can run up to 200MHz/CL3. The -6 parts can run up to 166MHz/CL3. The -7/-7S parts can run
up to 143MHz/CL3. And the grade of -7S with tRP = 18nS.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle.
The multiple bank nature enables interleaving among internal banks to hide the precharging time.By
having a programmable Mode Register, the system can change burst length, latency cycle, interleave
or sequential burst to maximize its performance. W9864G6IH is ideal for main memory in high
performance applications.
2. FEATURES
3.3V± 0.3V for -5/-6 speed grades power supply
2. 7V~3.6V for -7/-7S speed grades power supply
1,048,576 words × 4 banks × 16 bits organization
Self Refresh Current: Standard and Low Power
CAS Latency: 2 & 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Byte data controlled by LDQM, UDQM
Auto-precharge and controlled precharge
Burst read, single write operation
4K refresh cycles/64mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS compliant
Publication Release Date:Mar. 31, 2008
-3-
Revision A05

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]