W48S87-04(1999) 查看數據表（PDF） - Cypress Semiconductor
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W48S87-04 Datasheet PDF : 21 Pages
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PRELIMINARY
W48S87-04
2.5V DC Electrical Characteristics (CPU3.3#_2.5 Input = 1) (continued)
TA = 0°C to +70°C, VDD1:3 = 3.3V±5% (3.135–3.456V), VDDL1:2 = 2.5V±5% (2.375–2.625V)
Parameter
Description
Test Condition
Min.
Clock Outputs
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
2.2
IOL
Output Low Current
CPU0:3[10]
VOL = 1.25V
45
IOAPIC
VOL = 1.25V
55
IOH
Output High Current
CPU0:3[10]
VOH = 1.25V
40
IOAPIC
VOH = 1.25V
50
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
LIN
Input Pin Inductance
Serial Input Port
Except X1 and X2
VIL
Input Low Voltage
VIH
Input High Voltage
VDD = 2.5V
VDD = 2.5V
0.7VDD
Typ.
70
85
65
80
Max.
Unit
50
mV
V
105
mA
130
95
mA
120
5
pF
6
pF
7
nH
0.3VDD
V
V
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0)
TA = 0°C to +70°C, VDD1:3 = VDD1:3 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz CPU = 60 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
tP
Period
Measured on rising edge at 1.5V
15
16.7
ns
f
Frequency, Actual
Determined by PLL divider ratio
66.8
59.876
MHz
tH
High Time
Duration of clock cycle above 2.4V
5.2
6
ns
tL
Low Time
Duration of clock cycle below 0.4V
5
5.8
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
41
4 V/ns
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
41
4 V/ns
tD
Duty Cycle
Measured on rising and falling edge at 45
1.5V
55 45
55 %
tJC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Max-
250
imum difference of cycle time between
two adjacent cycles.
250 ps
tSK
Output Skew
Measured on rising edge at 1.5V
250
250 ps
fST
Frequency Stabilization Assumes full supply voltage reached
3
from Power-up (cold within 1 ms from power-up. Short cy-
start)
cles exist prior to frequency stabiliza-
tion.
3 ms
Zo
AC Output Impedance Average value during switching transi- 15 20 30 15 20 30 Ω
tion. Used for determining series termi-
nation value.
16
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