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W48S87-72X 查看數據表(PDF) - Cypress Semiconductor

零件编号
产品描述 (功能)
比赛名单
W48S87-72X
Cypress
Cypress Semiconductor Cypress
W48S87-72X Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
W48S87-72
How To Use the Serial Data Interface
Electrical Requirements
Figure 3 illustrates electrical characteristics for the serial inter-
face bus used with the W48S87-72. Devices send data over
the bus with an open drain logic output that can (a) pull the bus
line LOW, or (b) let the bus default to logic 1. The pull-up resis-
tors on the bus (both clock and data lines) establish a default
logic 1. All bus devices generally have logic inputs to receive
data.
Although the W48S87-72 is a receive-only device (no data
write-back capability), it does transmit an acknowledgedata
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration to-
tal bus line capacitance.
9''
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Figure 3. Serial Interface Bus Electrical Characteristics
9

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