LC8905V 查看數據表（PDF） - SANYO -> Panasonic

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LC8905V

Digital Audio Interface Receiver

SANYO -> Panasonic 

LC8905V

Microprocessor Interface (SCLK/CL, XLAT/CE, SWDT/DI, SRDT/DO, DQSY/LD)

1. Data input and output addresses are allocated as follows:

Data input or output

Data input

C bit output

Subcode Q, ID output

Figure 2: Microprocessor Interface Timing 1

B0 B1 B2 B3 A0 A1 A2 A3

F7 1 1 1 0 1 1 1 1

F8 0 0 0 1 1 1 1 1

F9 1 0 0 1 1 1 1 1

Figure 3: Microprocessor Interface Timing 2

B0 B1 B2 B3 A0 A1 A2 A3

EA 0 1 0 1 0 1 1 1

E9 1 0 0 1 0 1 1 1

E8 0 0 0 1 0 1 1 1

2. The input command codes control the following settings:

• System stop

• Data input pin settings

• Input bi-phase data output selection

• Validity flag output selection

• Audio data output format setting

DI1: Stops VCO operation and thus stops the system.

DI1

System

L

Operating

H

Stopped

DI2: Selects which input data to demodulate.

DI2

Data demodulation input

L

DIN1

H

DIN2

DI3 and DI4: Select the E/DOUT pin output.

DI3

DI4

E/DOUT

L

L

H

Emphasis Validity

data output flag output

H

L

H

DIN1 input DIN2 input

data output data output

DI5 and DI6: Set the audio data output format.

DI5

DI6

DATAOUT

L

H

L

H

L

H

16-bit right- 20-bit right- 20-bit right- 20-bit left-

justified

justified

justified

justified

MSB first LSB first MSB first MSB first

All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used.

No. 5237-12/16

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