CXD1915R 查看數據表（PDF） - Sony Semiconductor

零件编号

产品描述 (功能)

比赛名单

CXD1915R

Digital Video Encoder

Sony Semiconductor 

CXD1915R

4. SYSCLK, PDCLK, BF, CSYNC, HSYNC, VSYNC, FID

SYSCLK

PDCLK

VSYNC∗1

HSYNC∗1

FID∗1

CSYNC

BF

fSYSCLK

tPWHCLK

tPWLCLK

tPDCLKD

tCOD

tCOH

tPDCLKD

∗1 In master mode

Item

SYSCLK clock rate

SYSCLK pulse width Low

SYSCLK pulse width High

PDCLK delay time from SYSCLK

Control output delay time from SYSCLK

Control output hold time from SYSCLK

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Symbol

fSYSCLK

tPWLCLK

tPWHCLK

tPDCLKD∗

tCOD∗

tCOH∗

Min.

11

11

3

Typ.

27

Max. Unit

MHz

ns

ns

20

ns

26

ns

ns

∗ CL = 35pF

5. 8-bit mode

(1) Pixel data interface

SYSCLK

PD0 to PD7

tPDS

tPDH

Item

Pixel data setup time to SYSCLK

Pixel data hold time to SYSCLK

(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)

Symbol

tPDS

tPDH

Min.

11

0

– 11 –

Typ.

Max. Unit

ns

ns

Share Link: