XRD8799 查看數據表（PDF） - Exar Corporation

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产品描述 (功能)

比赛名单

XRD8799

LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX

Exar Corporation 

XRD8799

LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX

REV. 1.00

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FIGURE 7. DNL MEASUREMENT ON PRODUCTION

TESTER

Analog

Input

DNL

LSB

Output

Codes

(N) Code Width = V(N+1) - V(N)

LSB = [ VREF(+) - VREF(-) ] / 1024

DNL(N) = [ V(N+1) - V(N) ] - LSB

V(N+1)

V(N)

N+1

N

N-1

Figure 8 shows the zero scale and full scale error

terms.

Figure 9 gives a visual definition of the INL error. The

chart shows a 3-bit converter transfer curve with

greatly exaggerated DNL errors to show the deviation

of the real transfer curve from the ideal one.

After a tester has measured all the transition voltag-

es, the computer draws a line parallel to the ideal

transfer line. By definition the best fit line makes

equal the positive and the negative INL errors. For ex-

ample, an INL error of -1 to +2 LSB's relative to the

Ideal Line would be +1.5 LSB's relative to the best fit

line.

FIGURE 9. INL ERROR CALCULATION

The formulas for Differential Non-Linearity (DNL), In-

tegral Non-Linearity (INL) and zero and full scale er-

rors (EZS, EFS) are:

DNL (001) = V002 - V001 - LSB

:::

DNL (3FE) = V3FF - V3FE - LSB

EFS (full scale error) = V3FF - [VREF(+) -1.5 * LSB]

EZS (zero scale error) = V001 - [VREF(-) + 0.5 * LSB]

FIGURE 8. REAL A/D TRANSFER CURVE

Output

Codes

7

Real Transfer Line

6

Best Fit Line

5

EFS

INL

4

3

Ideal Transfer Line

2

1

LSB

DIGITAL

CODES

0.5 ∗ LSB

EZS

002

001

000

VREF(-)

V001

V002

1.5 ∗ LSB

EFS

3FF

3FE

V3FE

V3FF

V

VREF(+)

Analog Input (Volt)

EZS

1.2 CLOCK AND CONVERSION TIMING

A system will clock the XRD8799 continuously or it

will give clock pulses intermittently when a conversion

is desired. The timing of Figure 10a shows normal

operation, while the timing of Figure 10b keeps the

XRD8799 in balance and ready to sample the analog

input.

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