XRD87L99 查看數據表（PDF） - Exar Corporation
零件编号
产品描述 (功能)
比赛名单
XRD87L99 Datasheet PDF : 23 Pages
| |||
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
xr
ELECTRICAL CHARACTERISTICS AVDD = DVDD = 3 V, FS = 2 MHZ (50% DUTY CYCLE), VREF(+) = 2.6, VREF(-) = AGND,
TA = 25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS TEST CONDITIONS/COMMENTS
Clock to WR Hold Time
tCLKH2
0
ns
Power Down Time1
tPD
300
ns
Power Up Time1
tPU
200
ns
Data Enable Delay
tDEN
14
16
ns
Data High Z Delay
tDHZ
4
6
ns
Pipeline Delay (Latency)
1.5
cycles
POWER SUPPLIES 8
Power Down (IDD)
IPD-DD
0.01
0.10
mA PD=High, CLK High or Low
Operating Voltage (AVDD, DVDD) VDD
2.7
3.0
3.6
V
Current (AVDD + DVDD)
IDD
7
10
mA PD=Low (Normal Mode)
VDD =3 V
NOTES:
1 Guaranteed. Not tested.
2 Tester measures code transition voltages by dithering the voltage of the analog input (VIN). The difference between
the measured code width and the ideal value (VREF/1024) is the DNL error. The INL error is the maximum distance
(in LSBs) from the best fit line to any transition voltage.
3 See VIN input equivalent circuit.
4 Clock specification to meet aperture specification (tAP). Actual rise/fall time can be less stringent with no loss of
accuracy.
5 Specified values guarantee functional device. Refer to other parameters for accuracy.
6 System can clock the XRD87L99 with any duty cycle as long as all timing conditions are met.
7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to
zero or full scale output.
8 DVDD and AVDD are connected through the silicon substrate. Connect together at the package.
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE
7
Share Link: 