RTL8196 查看數據表（PDF） - Realtek Semiconductor

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RTL8196

IEEE 802.11n AP/ROUTER NETWORK PROCESSOR WITH EEE

Realtek Semiconductor 

RTL8196C

Datasheet

6.3. SPI Flash Controller

The SPI flash controller is a new design and incorporates new features.

6.3.1. Features

• Targeted SPI Flash Frequency: Up to 78MHz (when the SDRAM clock is 156MHz)

• In addition to a programmed I/O interface, also supports a memory-mapped I/O interface for read

operations

• Supports Read and Fast Read in memory-mapped I/O mode

6.4. Software Register Definition

6.4.1. Memory Control Register (MCR) (0xB800_1000)

This register does not provide byte access.

k Table 4. Memory Control Register (MCR) (0xB800_1000)

lte Bit Name

Description

31 DRAMTYPE

Report the Hardware Strapping Initial Value for DRAM Type

0: SDR DRAM

1: Reserved

L 30 BOOTSEL

Report the Hardware Strapping Initial Value for Boot Flash Type

a IA 0: NORflash

1: SPI flash

29 IPREF

Enable Instruction Prefetch Function

T 0: Disable prefetch (also resets buffer status)

e N N 1: Enable prefetch (4 words)

R E IO 28 DPREF

Enable Data Prefetch Function

0: Disable prefetch (also resets buffer status)

T 1: Enable prefetch (4 words)

ID A 27 IPREF_MODE

Choose Instruction Prefetch Mode

R 0: Old prefetch mechanism

1: New prefetch mechanism

F O 26 DPREF_MODE

Choose Data Prefetch Mode

N P 0: Old prefetch mechanism

1: New prefetch mechanism

R 25 BOOTSEL2

Report the Hardware Strapping Initial Value for Boot Source

O O 0: Flash Type (NOR or SPI Flash)

C C 1: Reserved

for ZTE 24:0 Reserved

Reserved

Mode Default

R

0B

R

0B

RW 0B

RW 0B

RW 0B

RW 0B

R

0B

R

0B

IEEE 802.11n AP/Router Network Processor with EEE 13

Track ID: JATR-2265-11 Rev. 0.7

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