datasheetbank_Logo
数据手册搜索引擎和 Datasheet免费下载 PDF

TDA7503 查看數據表(PDF) - STMicroelectronics

零件编号
产品描述 (功能)
比赛名单
TDA7503 Datasheet PDF : 30 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TDA7503
All values are valid on the entire operation range unless otherwise specified.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
VDD
3.3V Power Supply Voltage
Min.
Typ.
Max.
Unit
3.15
3.3
3.45
V
CURRENT CONSUMPTION
Symbol
Parameter
Idd Maximum current
Note: 42MHz internal DSP clock
PLL CHARACTERISTICS
Symbol
Parameter
Lock Time (note1)
Fvco VCO Frequency (note 2)
Note: 1. Depending on VCO output frequency.
2. Fdsp = Fvco/2 when PLL is running
Test Condition
Min. Typ. Max. Unit
290 325 mA
Test Condition
Min.
70
Typ.
1
Max.
3
140
Unit
ms
MHz
OSCILLATOR CHARACTERISTICS
Symbol
Parameter
Fosc Max Oscillator Frequency (XTI)
When PLL is enabled see constraints for Internal Clocks.
Test Condition
Min.
8
Typ.
10.5
Max.
12.5
Unit
MHz
DSP and MICRO CLOCKS
Symbol
Characteristics
fDSP_MAX Maximum DSP Internal Operation
Frequency (dclk)
fµP_MAX Maximum µP (MX51) Internal
Operation Frequency (mclk)
Test Conditions
Min.
42
Typ.
Max.
Unit
MHz
21
MHz
INTERNAL CLOCKS
Symbol
Characteristics
Fdsp Internal DSP Clock Cycle Frequency (dclk)
Test Conditions
Expression
M-----2-F------D--F---F-e---x--t
fµP Internal µP (MX51) Clock Cycle Frequency (mclk)
M-----4-F------D--F---F-e---x--t
Icyc_DSP DSP Machine Cycle Time
Icyc_µP µP (MX51) Machine Cycle Time
Notes: 1. DF is PLL input devide factor, bits IDF [4:0] of PLL control register one.
2. MF is PLL multiply devide factor, bits MP [6:0] of PLL control register zero.
3. 1 cyc. µP is given for a basic instruction.
4. Fext = External Crystal Oscillator frequency
dclk
4mclk
10/30

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]