ST16C450IJ44 查看數據表（PDF） - Exar Corporation
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ST16C450IJ44 Datasheet PDF : 28 Pages
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ST16C450
SYMBOL DESCRIPTION
Symbol
-IOR
-IOW
INT
CSOUT
-BAUDOUT
-DDIS
-OP1
RESET
RCLK
Rev. 4.20
Pin
Signal
40 44 48 type
Pin Description
21 24 19
I Read data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the ST16C450 data bus to the
CPU.
18 20 16
I Write data strobe (active low strobe). A logic 0 on this pin
transfers the contents of the CPU data bus to the addressed
internal register.
30 33 30
O Interrupt Request (active high). Interrupts are enabled in the
interrupt enable register (IER), and when an interrupt con-
dition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
24
27
23
O Chip select out. A high on this pin indicates that the
ST16C450 has been enabled by the chip select pin.
15
17
12
O Baud Rate Generator Output. This pin provides the 16X
clock of the selected data rate from the baud rate generator.
The RCLK pin must be connected externally to -BAUDOUT
when the receiver is operating at the same data rate.
23
26
22
O Drive Disable. This pin goes to a logic 0 when the external
CPU is reading data from the ST16C450. This signal can be
used to disable external transceivers or other logic func-
tions.
34
38
34
O Output-1 (User Defined) - See bit-2 of modem control
register (MCR bit-2).
35 39 35
I Reset. (active high) - A logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See ST16C450 External Reset Conditions for initial-
ization details.)
9
10
5
I Receive Clock Input. This pin is used as external 16X clock
input to the receiver section. External connection to -
Baudout pin is required in order to utilize the internal baud
rate generator.
5
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