SM5852CS 查看數據表（PDF） - Nippon Precision Circuits

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产品描述 (功能)

比赛名单

SM5852CS

Dynamic Range Compression LSI

Nippon Precision Circuits  

INPUT/OUTPUT TIMING

Input Timing

LRCI

BCKI

MSB

DI

SM5852CS

Lch

LSB

MSB

Rch

LSB

There must be a minimum of 16 BCKI clock cycles to read in a single word of data.

Data on DI is input in sync with the falling edge of BCKI in 16-bit serial, MSB first, 2s complement

format.

Output Timing

LRCO

BCKO

DOUT ,, MSB

Lch

,,,, LSB

MSB

Shaded areas represent intervals of invalid data.

Rch

,, LSB

NIPPON PRECISION CIRCUITS—16

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