XRT73L00A 查看數據表（PDF） - Exar Corporation

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XRT73L00A

E3/DS3/STS-1 LINE INTERFACE UNIT

Exar Corporation 

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PIN DESCRIPTION

PIN #

SYMBOL

30

LCV/(RCLK2)

31

RCLK1

32

RNEG

33

RPOS

34

ICT

XRT73L00A

E3/DS3/STS-1 LINE INTERFACE UNIT

REV. 2.0.1

TYPE

O

O

O

O

I

DESCRIPTION

Line Code Violation Indicator/Receive Clock Output pin 2:

The function of this pin depends upon whether the XRT73L00A is operating in

the HOST Mode, the Hardware Mode or User selection.

HOST Mode - Line Code Violation Indicator Output:

If the XRT73L00A is configured to operate in the HOST Mode, then this pin func-

tions as the LCV output pin by default. However, by using the on-chip Command

Registers, this pin can be configured to function as the second Receive Clock

signal output pin RCLK2.

Hardware Mode - Receive Clock Output pin 2:

This output pin is the Recovered Clock signal from the incoming line signal. The

receive section of the XRT73L00A outputs data via the RPOS and RNEG output

pins on the rising edge of this clock signal.

NOTE: If the XRT73L00A is operating in the HOST Mode and this pin is config-

ured to function as the additional Receive Clock signal output pin, then the

XRT73L00A can be configured to update the data on the RPOS and RNEG out-

put pins on the falling edge of this clock signal.

Receive Clock Output pin 1:

This output pin is the Recovered Clock signal from the incoming line signal. The

receive section of the XRT73L00A outputs data via the RPOS and RNEG output

pins on the rising edge of this clock signal.

NOTE: If the XRT73L00A is operating in the HOST Mode, the device can be con-

figured to update the data on the RPOS and RNEG output pins on the falling

edge of this clock signal.

Receive Negative Pulse Output:

This output pin pulses “High” whenever the XRT73L00A has received a Negative

Polarity pulse in the incoming line signal at the RTIP/RRING inputs.

NOTES:

1. If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in

the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not

reflected at this output.

2. This output pin is inactive if the XRT73L00A has been configured to

operate in the Single-Rail Mode.

Receive Positive Pulse Output:

This output pin pulses “High” whenever the XRT73L00A has received a Positive

Polarity pulse in the incoming line signal at the RTIP/RRING inputs.

NOTE: If the B3ZS/HDB3 Decoder is enabled, the zero suppression patterns in

the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are not

reflected at this output.

In-Circuit Test Input:

Setting this input pin “Low” causes all digital and analog outputs to go into a

high-impedance state in order to permit in-circuit testing. Set this pin “High” for

normal operation.

NOTE: This pin is internally pulled “High”.

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