74ABT16821ADL 查看數據表（PDF） - NXP Semiconductors.

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74ABT16821ADL

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

NXP Semiconductors. 

NXP Semiconductors

11. Waveforms

74ABT16821A

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

VI

nCP

0V

VOH

nQx

VOL

1 / fmax

VM

tWH

tPHL

VM

tWL

VM

VM

tPLH

VM

001aae858

Fig 5.

VM = 1.5 V

VOL and VOH are typical voltage output levels that occur with the output load.

Propagation delay, clock input to output, clock pulse width, and maximum clock frequency

VI

nOE input

GND

3.5 V

output

LOW-to-OFF

OFF-to-LOW

VOL

VOH

output

HIGH-to-OFF

OFF-to-HIGH

GND

VM

tPLZ

tPZL

tPHZ

VOL + 0.3 V

VOH − 0.3 V

VM

tPZH

VM

outputs

enabled

outputs

disabled

outputs

enabled

001aal294

Fig 6.

VM = 1.5 V

VOL and VOH are typical voltage output levels that occur with the output load.

3-state output enable time to HIGH-level and output disable time from HIGH- level

74ABT16821A_3

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 03 — 16 March 2010

© NXP B.V. 2010. All rights reserved.

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