74LS645 查看數據表（PDF） - Fairchild Semiconductor

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比赛名单

74LS645

Octal Bus Transceiver

Fairchild Semiconductor 

August 1986

Revised March 2000

DM74LS645

Octal Bus Transceiver

General Description

These octal bus transceivers are designed for asynchro-

nous two-way communication between data buses. The

devices transmit data from the A bus to the B bus or from

the B bus to the A bus depending upon the level at the

direction control (DIR) input. The enable input (G) can be

used to disable the device so that the buses are effectively

isolated.

Features

s Bi-directional bus transceivers in high-density 20-pin

packages

s Hysteresis at bus inputs improves noise margins

s 3-STATE outputs

Ordering Code:

Order Number Package Number

Package Description

DM74LS645WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74LS645N

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Control

Inputs

G

L

L

H

H = HIGH Level

L = LOW Level

X = Irrelevant

DIR

L

H

X

DM74LS645

B data to A bus

A data to B bus

Isolation

© 2000 Fairchild Semiconductor Corporation DS009056

www.fairchildsemi.com

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