A617308V-15 查看數據表（PDF） - AMIC Technology

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A617308V-15

128K X 8 BIT HIGH SPEED CMOS SRAM

AMIC Technology 

Timing Waveforms (continued)

Read Cycle 4(1, 4, 7, 8)

CE2

DOUT

tCLZ 5

tACE

A617308 Series

tCHZ 5

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled, CE1= VIL and CE2= VIH

3. Address valid prior to or coincident with CE1 transition low.

4. OE = VIL.

5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

6. CE2 is high.

7. CE1 is low.

8. Address valid prior to or coincident with CE2 transition high.

Write Cycle 1(6)

(Write Enable Controlled)

Address

CE1

CE2

WE

DIN

DOUT

(4)

(4)

tAS1

tWC

tAW

tCW5

tWP2

tWR3

tDW

tWHZ7

tDH

tOW7

PRELIMINARY (January, 2000, Version 0.2)

7

AMIC Technology, Inc.

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