N
N+1
N+2
N+3
N+4
N+5
AIN
ENCODE
DIGITAL
OUTPUTS
tA = 1.0ns TYP
tOD = 12ns TYP
N–2
N–1
N
N+1
N+2
Figure 1. Timing Diagram
AD10242
TTL CLOCK
ENC
D11
f 10MHz
ENC
D10
D9
D8
AIN3
1/2
D7
D6
AIN2
AD10242
SHOWN
D5
D4
D3
AIN1
D2
D1
D0
ALL 5V SUPPLY PINS BYPASSED
TO GND WITH A 0.1F CAPACITOR
Figure 2. Equivalent Burn-In Circuit
EQUIVALENT CIRCUITS
AIN3
AIN2
AIN1
R4
200⍀
R3
100⍀
R2
21⍀
R1
79⍀
TO AD9632
Figure 3. Analog Input Stage
AVCC
AVCC
R1
17k⍀
ENCODE
R2
8k⍀
TIMING
CIRCUITS
AVCC
R1
17k⍀
R2
8k⍀
ENCODE
Figure 4. Encode Inputs
DVCC
CURRENT
MIRROR
VREF
DVCC
D0–D11
CURRENT
MIRROR
Figure 5. Digital Output Stage
REV. D
–7–