ADP3419 查看數據表（PDF） - ON Semiconductor
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ADP3419 Datasheet PDF : 10 Pages
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ADP3419
PIN ASSIGNMENT
Pin No.
1
Mnemonic
IN
2
SD
3
DRVLSD
4
CROWBAR
5
VCC
6
DRVL
7
GND
8
SW
9
DRVH
10
BST
Description
Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling
this pin low turns on the low-side driver; pulling it high turns on the high-side driver.
Shutdown Input. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Synchronous Rectifier Shutdown Input. When low, DRVL is forced low; when high, DRVL is enabled
and controlled by IN and by the adaptive overlap protection control circuitry.
Crowbar Input. When high, DRVL is forced high regardless of the high-side MOSFET switch condition.
Input Supply. This pin should be bypassed to GND with a 4.7 mF or larger ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Input. This pin is connected to the buck-switching node, close to the upper MOSFET’s
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the
switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins
holds this bootstrapped voltage for the high-side MOSFET as it is switched.
ELECTRICAL CHARACTERISTICS VCC = SD = 5.0 V, BST = 4.0 V to 26 V. TA = 0°C to 100°C, unless otherwise noted All limits at
temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Parameter
Symbol
Conditions
Min Typ Max Unit
LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR)
Input Voltage High
Input Voltage Low
Input Current
DRVLSD Propagation Delay Time
HIGH-SIDE DRIVER
VIH
VIL
IIN
tpdl DRVLSD,
tpdh DRVLSD
Inputs = 0 V or 5.0 V
CLOAD = 3 nF, Figure 3
2.0
V
0.8
V
−1.0
+1.0 mA
20
ns
Output Resistance, Sourcing Current
BST − SW = 4.6 V
1.7 3.3
W
Output Resistance, Sinking Current
BST − SW = 4.6 V
0.8 2.3
W
Transition Times
Propagation Delay Times (Note 1)
LOW-SIDE DRIVER
trDRVH
tfDRVH
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
14
35
ns
11
25
tpdhDRVH
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
15
32
70
ns
tpdlDRVH
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
28
60
Output Resistance, Sourcing Current
1.7 3.3
W
Output Resistance, Sinking Current
0.8 2.3
W
Transition Times
Propagation Delay Times (Note 2)
SW Transition Timeout (Note 1 and 2)
Zero-Crossing Threshold
SUPPLY
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
tSWTO
VZC
CLOAD = 3 nF, Figure 4
CLOAD = 3 nF, Figure 4
CLOAD = 3 nF, Figure 4
CLOAD = 3 nF, Figure 4
BST − SW = 4.6 V
13
30
ns
11
25
25
48
ns
16
30
150 350 600
ns
1.0
V
Supply Voltage Range
Supply Current
Normal Mode
Shutdown Mode
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
(Note 3)
VCC
ISYS(NM)
ISYS(SD)
ICC + IBST, IN = 0 V or 5.0 V
ICC + IBST, SD = 0 V
VCC rising
VCC falling
4.6
6.0
V
0.8 1.5
mA
325 600
mA
3.8 4.25 4.5
V
50 120
mV
1. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%.
2. The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO.
3. Guaranteed by characterization, not production tested.
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