AS4LC4M4883C 查看數據表（PDF） - Austin Semiconductor
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AS4LC4M4883C Datasheet PDF : 20 Pages
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AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
NOTE:
READ CYCLE
V IH
RAS VIL
tCRP
tRC
tRAS
tRCD
tCSH
tRSH
tCAS
tRP
tRRH
CAS
V
V
IH
IL
,,,, ,,,, ,, , ADDR
V
V
IH
IL
, , ,, , ,,,,,,,, WE VIH
, VIL
tASR
tRAD
tRAH
ROW
tWRP tWRH
NOTE 1
tAR
tASC
tACH
tRAL
tCAH
tRCS
COLUMN
tAA
tRAC
tRCH
NOTE 2
ROW
DQ VVOOHL
,,,,,,,,,,,,,,,,,,,,,,,,, OE
V
V
IH
IL
OPEN
tCAC
tCLZ
t OE
tOFF
VALID DATA
t OD
OPEN
DON’T CARE
UNDEFINED
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
2. tOFF is referenced from rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
TIMING PARAMETERS
SYM
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCLZ
tCRP
tCSH
tOD
tOE
tOFF
-6
MIN MAX
30
15
45
0
0
15
10
12 10,000
0
5
50
0
15
15
0
15
-7
MIN MAX
35
15
50
0
0
20
15
15 10,000
0
5
55
0
15
20
0
15
-8
MIN MAX UNITS
40 ns
20
ns
60
ns
0
ns
0
ns
20 ns
15
ns
20 10,000 ns
0
ns
5
ns
60
ns
20 ns
20 ns
0
20 ns
SYM
tRAC
tRAD
tRAH
tRAL
tRAS
tRC
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
-6
MIN MAX
60
15 30
10
30
60 10,000
110
16 45
0
0
40
0
10
10
10
-7
MIN MAX
70
15
35
10
35
70 10,000
130
16
50
0
0
50
0
12
10
10
-8
MIN MAX UNITS
80 ns
15
40 ns
10
ns
40
ns
80 10,000 ns
150
ns
20
60 ns
0
ns
0
ns
60
ns
0
ns
15
ns
10
ns
10
ns
AS4LC4M4
Rev. 11/97
DS000022
2-81
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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