CD4070BE 查看數據表（PDF） - Harris Semiconductor
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CD4070BE Datasheet PDF : 7 Pages
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Functional Diagrams
CD4070B
1
A
2
J=A⊕B B
K=C⊕D C 5
6
M=G⊕H D
L = E⊕ F
VSS = 7
VDD = 14
8
E
9
F
G 12
13
H
CD4070B, CD4077B
3
J
4
K
10
L
11 M
CD4077B
1
A
2
B
J =A⊕B
5
K=C⊕D C 6
D
M=G⊕H E 8
L =E⊕F F 9
G 12
13
H
3
J
4
K
10
L
11 M
VDD
B†
2(5, 9, 12)
A†
1(6, 8, 13)
p
nn
VSS
p
VDD
p
n
VSS
VDD
† INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
VDD
p
p
p
J
n
3(4, 10, 11)
n
VSS
VDD
p
B†
p
2(5, 9, 12)
nn
n
VSS
p
VDD
A†
p
n
1(6, 8, 13)
n
VSS
VDD
† INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
VDD
p
J
3(4, 10, 11)
n
VSS
VSS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B
(1 OF 4 IDENTICAL GATES)
VSS
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES)
CD4070B TRUTH TABLE (1 OF 4 GATES)
A
B
J
0
0
0
1
0
1
0
1
1
1
1
0
NOTE:
1 = High Level
0 = Low Level
J=A⊕B
CD4077B TRUTH TABLE (1 OF 4 GATES)
A
B
J
0
0
1
1
0
0
0
1
0
1
1
1
NOTE:
1 = High Level
0 = Low Level
J=A⊕B
2
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