CS51311 查看數據表（PDF） - ON Semiconductor

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CS51311

Synchronous CPU Buck Controller for 12 V and 5.0 V Applications

ON Semiconductor 

CS51311

relation to the crossover frequency, since transient response

is handled by the ramp signal loop. The main purpose of this

“slow” feedback loop is to provide DC accuracy. Noise

immunity is significantly improved, since the error

amplifier bandwidth can be rolled off at a low frequency.

Enhanced noise immunity improves remote sensing of the

output voltage, since the noise associated with long

feedback traces can be effectively filtered. The COMP pin

is the output of the error amplifier and a capacitor to GND

compensates the error amplifier loop. Additionally, through

the built−in offset on the PWM Comparator non−inverting

input, the COMP pin provides the hiccup timing for the

Overcurrent Protection, the Soft Start function that

minimizes inrush currents during regulator power−up and

switcher output enable.

Startup

The CS51311 provides a controlled startup of regulator

output voltage and features Programmable Soft Start

implemented through the Error Amp and external

Compensation Capacitor. This feature, combined with

overcurrent protection, prevents stress to the regulator

power components and overshoot of the output voltage

during startup.

As power is applied to the regulator, the CS51311

Undervoltage Lockout circuit (UVL) monitors the IC’s

supply voltage (VCC) which is typically connected to the

+12 V output of the AC−DC power supply. The UVL circuit

prevents the NFET gates from being activated until VCC

exceeds the 8.4 V (typ) threshold. Hysteresis of 300 mV

(typ) is provided for noise immunity. The Error Amp

Capacitor connected to the COMP pin is charged by a 30 μA

current source. This capacitor must be charged to 1.1 V (typ)

so that it exceeds the PWM comparator’s offset before the

V2 PWM control loop permits switching to occur.

When VCC has exceeded 8.4 V and COMP has charged to

1.1 V, the upper Gate driver (GATE(H)) is activated, turning

on the upper FET. This causes current to flow through the

output inductor and into the output capacitors and load

according to the following equation:

I + (VIN * VOUT)

T

L

GATE(H) and the upper NFET remain on and inductor

current ramps up until the initial pulse is terminated by either

the PWM control loop or the overcurrent protection. This

initial surge of in−rush current minimizes startup time, but

avoids overstressing of the regulator’s power components.

The PWM comparator will terminate the initial pulse if

the regulator output exceeds the voltage on the COMP pin

plus the 1.1 V PWM comparator offset prior to the drop

across the current sense resistor exceeding the current limit

threshold. In this case, the PWM control loop has achieved

regulation and the initial pulse is then followed by a constant

off time as programmed by the COFF capacitor. The COMP

capacitor will continue to slowly charge and the regulator

output voltage will follow it, less the 1.1 V PWM offset, until

it achieves the voltage programmed by the DAC’s VID

input. The Error Amp will then source or sink current to the

COMP cap as required to maintain the correct regulator DC

output voltage. Since the rate of increase of the COMP pin

voltage is typically set much slower than the regulator’s slew

capability, inrush current, output voltage, and duty cycle all

gradually increase from zero. (See Figures 9, 10, and 11).

Channel 1 − Regulator Output Voltage (1.0 V/div)

Channel 2 − COMP Pin (1.0 V/div)

Channel 3 − VCC (10 V/div)

Channel 4 − Regulator Input Voltage (5.0 V/div)

Figure 9. Normal Startup (2.0 ms/div)

Channel 1 − Regulator Output Voltage (1.0 V/div)

Channel 2 − Inductor Switching Node (5.0 V/div)

Channel 3 − VCC (10 V/div)

Channel 4 − Regulator Input Voltage (5.0 V/div)

Figure 10. Normal Startup Showing Initial Pulse

Followed by Soft Start (20 ms/div)

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