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DM81LS95 查看數據表(PDF) - Fairchild Semiconductor

零件编号
产品描述 (功能)
比赛名单
DM81LS95
Fairchild
Fairchild Semiconductor Fairchild
DM81LS95 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
DC Electrical Characteristics DM81LS96A
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
VOH
HIGH Level Output Voltage
VCC = Min, IOH = Max
2.7
VIL = Max, VIH = Min
VOL
LOW Level Output Voltage
VCC = Min, IOL = Max
IOL = Max, VIH = Min
IOL = 12 mA, VCC = Min
II
Input Current @ Max
VCC = Max, VI = 7V
Input Voltage
IIH
HIGH Level Input Current
IIL
LOW Level Input Current
VCC = Max, VI = 2.7V
VCC = Max VI = 0.5V
VI = 0.4V
A (Note 9)
A (Note 10)
G
IOZH
Off-State Output Current
with HIGH Level Output
Voltage Applied
VCC = Max, VO = 2.4V
VIH = Min, VIL = Max
IOZL
Off-State Output Current
with LOW Level Output
Voltage Applied
VCC = Max, VO = 0.4V
VIH = Min, VIL = Max
IOS
Short Circuit
VCC = Max
20
Output Current
(Note 11)
ICC
Supply Current
Note 8: All typicals are at VCC = 5V, TA = 25°C.
Note 9: Both G inputs are at 2V.
VCC = Max (Note 10)
Note 10: Both G inputs are at 0.4V.
Note 11: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Typ
Max
(Note 8)
1.5
0.5
0.4
0.1
20
20
50
50
20
20
100
13
21
AC Electrical Characteristics DM81LS96A
VCC = 5V, TA = 25°C
RL = 667
Symbol
Parameter
CL = 50 pF
CL = 150 pF
Min
Max
Min
Max
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
10
16
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
17
30
tPZH
Output Enable Time
to HIGH Level Output
15
30
tPZL
Output Enable Time
to LOW Level Output
35
45
tPHZ
Output Disable Time
20
from HIGH Level Output (Note 12)
tPLZ
Output Disable Time
27
from LOW Level Output (Note 12)
Note 12: CL = 5 pF.
Units
V
V
V
mA
µA
µA
µA
µA
mA
mA
Units
ns
ns
ns
ns
ns
ns
5
www.fairchildsemi.com

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