TDA7580(2002) 查看數據表（PDF） - STMicroelectronics

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TDA7580
(Rev.:2002)

FM/AM digital IF sampling processor

STMicroelectronics 

I2C TIMING

Figure 11. DSP and RDS I2C BUS Timings.

TDA7580

Symbol

Parameter

Test Condition

FSCL

tBUF

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tR

tF

tSU;STO

tSU:DAT

Cb

SCLl clock frequency

Bus free between a STOP and

Start Condition

Hold time (repeated) START

condition. After this period, the

first clock pulse is generated

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated start

condition

DATA hold time

Rise time of both SDA and SCL

signals

Fall time of both SDA and SCL

signals

Set-up time for STOP condition

Data set-up time

Capacitive load for each bus line

Cb in pF

Cb in pF

Standard Mode Fast Mode

I2C BUS

I2C BUS

Unit

Min. Max. Min. Max.

0

100

0

400 kHz

4.7

–

1.3

–

µs

4.0

–

0.6

–

µs

4.7

–

1.3

–

µs

4.0

–

0.6

–

µs

4.7

–

0.6

–

µs

0

–

0

0.9

µs

–

1000 20+ 300

ns

0.1Cb

–

300 20+ 300

ns

0.1Cb

4

–

0.6

–

µs

250

--

--

100

ns

–

400

–

400

pF

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