TDA7580(2002) 查看數據表（PDF） - STMicroelectronics
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TDA7580 Datasheet PDF : 31 Pages
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TDA7580
PIN DESCRIPTION (continued)
N°
Name
45 TST2_SCKR
46 TST3_LRCKR
47 VDD
48 GND
49 DBCK0
50 DBIN0
51 DBRQ0
52 DBOUT0
53 GNDH
54 VDDH
55 DBCK1
56 DBIN1
57 DBRQ1
Type
Description
Notes
B SAI0 Transmit bit clock; SAI1 Receive 5V tolerant
and Transmit bit clock. Or Test selection DSP0 GPIO6
pin in Test Mode
With internal pull_up, on
at reset
B SAI0 Transmit LeftRight clock; SAI1
DSP0 GPIO7
Receive and Transmit bit clock. Or Test 5V tolerant
selection pin in Test Mode
With internal pull_up, on
at reset
P Digital Core Power Supply
1.8V
G Digital Core Power Ground
B Debug Port Clock of DSP0 (DBCK0)
DSP0 GPIO9
5V tolerant
With internal pull_down,
on at reset
B Debug Port Data Input of DSP0 (DBIN0) DSP0 GPIO11
5V tolerant
With internal pull_down,
on at reset
B Debug Port Request of DSP0 (DBRQ0) DSP0 GPIO
5V tolerant
With internal pull_up, on
at reset
B Debug Port Data Output of DSP0
(DBOUT0)
DSP0 GPIO10
5V tolerant
With internal pull_up, on
at reset
G 3.3V IO Ring Power Ground (Debug
Interface, GPIO)
P 3.3V IO Ring Power Supply (Debug
Interface, GPIO)
B DSP1 Debug Port Clock (DBCK1) if HS3I DSP1 GPIO9
master mode, else High Speed
5V tolerant
Synchronous Serial Interface (HS3I)
Channel3 Data
With internal pull_down,
on at reset
B DSP1 GPIO or DSP1 Debug Port Data DSP1 GPIO11
In (DBIN1) if HS3I master mode, else
High Speed Synchronous Serial
Interface (HS3I) Channel2 Data i
5V tolerant
With internal pull_down,
on at reset
B DSP1 GPIO or DSP1 Debug Port
5V tolerant
Request (DBRQ1) if HS3I master mode, With internal pull_up, on
else High Speed Synchronous Serial
at reset
Interface (HS3I) Channel1 Data
After
Reset
Input
Input
Input
Input
Input
Input
Input
Input
Input
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