HSP50216 查看數據表（PDF） - Intersil

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HSP50216

Four-Channel Programmable Digital Downconverter

Intersil 

Block Diagram

μP

TEST

REGISTER

INPUT SELECT,

FORMAT,

DEMUX

HSP50216

LEVEL

DETECTOR

A(15:0)

ENIA

B(15:0)

ENIB

C(15:0)

ENIC

D(15:0)

ENID

CLK

RESET

SYNCI

SYNCO

INPUT SELECT,

FORMAT,

DEMUX

I

NCO/MIXER/CIC

Q

CHANNEL 0

FIR FILTERS,

AGC,

CARTESIAN-TO-POLAR

COORDINATE

CONVERTER

INPUT SELECT,

FORMAT,

DEMUX

INPUT SELECT,

FORMAT,

DEMUX

I

NCO/MIXER/CIC

Q

CHANNEL 1

I

NCO/MIXER/CIC

Q

BUS

ROUTING

CHANNEL 2

FIR FILTERS,

AGC,

CARTESIAN-TO-POLAR

COORDINATE

CONVERTER

FIR FILTERS,

AGC,

CARTESIAN-TO-POLAR

COORDINATE

CONVERTER

INPUT SELECT,

FORMAT,

DEMUX

I

NCO/MIXER/CIC

Q

CHANNEL 3

FIR FILTERS,

AGC,

CARTESIAN-TO-POLAR

COORDINATE

CONVERTER

SCLK

SYNCA

SDIA

SD2A

SYNCB

SDIB

SD2B

OUTPUT

SELECT,

FORMAT,

SERIALIZE

SYNCC

SDIC

SD2C

SYNCD

SDID

SD2D

P(15:0)

ADD(2:0)

μP INTERFACE

RD

or

RD/WR

WR

or

DSTRB

μP MODE

INTRPT

CE

2

FN4557.6

August 17, 2007

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