HD74LV161ARPEL 查看數據表（PDF） - Renesas Electronics

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HD74LV161ARPEL

Synchronous 4-bit Binary Counter (Synchronous Clear)

Renesas Electronics 

HD74LV161A

Switching Characteristics (cont)

Item

Maximum clock

frequency

Propagation

delay time

Setup time

Symbol

fmax

tPLH/tPHL

tPLH/tPHL

Count mode

tPLH/tPHL

Load mode

tPLH/tPHL

tPHL

tPHL

tsu

Ta = 25°C

Min Typ

80 130

55 85

— 8.3

— 10.8

— 8.7

— 11.2

— 11.0

— 13.5

— 7.5

— 10.5

— 8.9

— 11.2

— 8.4

— 10.9

5.5 —

8.0 —

7.5 —

2.5 —

Hold time

th

Pulse width

tw

1.0 —

5.0 —

5.0 —

Max

—

—

12.8

16.3

13.6

17.1

17.2

20.7

12.3

15.8

13.6

17.1

13.2

16.7

—

—

—

—

—

—

—

Ta = –40 to 85°C

Min

Max

70

—

50

—

1.0

15.0

1.0

18.5

1.0

16.0

1.0

19.5

1.0

20.0

1.0

23.5

1.0

14.5

1.0

18.0

1.0

16.0

1.0

19.5

1.0

15.5

1.0

19.0

6.5

—

9.5

—

9.0

—

2.5

—

1.0

—

5.0

—

5.0

—

Unit

MHz

ns

ns

ns

ns

Test

Conditions

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

VCC = 3.3 ± 0.3 V

FROM TO

(Input) (Output)

CLK

Q

CLK

Carry

CLK

Carry

ENT

Carry

CLR

Q

CLR

Carry

Data before CLK ↑

LOAD before CLK ↑

ENT, ENP before

CLK ↑

CLR inactive before

CLK ↑

CLK H or L

CLR L

Rev.4.00 Jun. 04, 2004 page 8 of 15

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