ICS9248F-107 查看數據表（PDF） - Integrated Circuit Systems

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ICS9248F-107

Frequency Timing Generator for PENTIUM II Systems

Integrated Circuit Systems 

Power Management Features:

PD# CPUCLK IOAPIC 3V66

0

LOW LOW LOW

PCI

PCI_F

REF.

48MHz

Osc

LOW LOW LOW OFF

VCOs

OFF

1

ON

ON

ON

ON ON

ON

ON ON

Note:

1. LOW means outputs held static LOW as per latency requirement next page.

2. On means active.

3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.

ICS9248-107

Power Management Requirements:

Signal

PD#

Signal State

1 (normal operation)

0 (power down)

Latency

No. of rising edges of

PCICLK

3mS

2max.

Note:

1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/

high to the first valid clock comes out of the device.

2. Power up latency is when PWR_DWN# goes inactive (high) to when the first valid clocks are dirven from the device.

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