76413DK8 查看數據表（PDF） - Fairchild Semiconductor
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76413DK8 Datasheet PDF : 11 Pages
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SABER Electrical Model
REV April 2002
template HUFA76413DK8T n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 8e-13, rs = 1.58e-2, trs1 = 1e-3, trs2 = 3e-6, xti = 3.2, cjo = 8e-10, tt = 3.2e-8, m = 0.54)
dp..model dbreakmod = (rs = 1.18, trs1 = 2e-3, trs2 = -2.6e-5)
dp..model dplcapmod = (cjo = 5.7e-10, isl =10e-30, nl =10, m = 0.87)
m..model mmedmod = (type=_n, vto = 1.68, kp = 2, is =1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.05, kp = 35, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.48, kp = 0.04, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.0, voff = -1.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.0, voff = -5.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.2)
DPLCAP
c.ca n12 n8 = 7.8e-10
c.cb n15 n14 = 9.8e-10
c.cin n6 n8 = 5.8e-10
10
RSLC2
5
RSLC1
51
LDRAIN
DRAIN
2
RLDRAIN
dp.dbody n7 n5 = model=dbodymod
ISCL
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
-
ESG
6
8
+
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 1.34e-9
l.lsource n3 n7 = 0.59e-9
LGATE
EVTEMP
GATE
1
RGATE + 18 - 6
9
20 22
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
EVTHRES
+ 19 -
8
CIN
50
RDRAIN
16
21
DBREAK
11
MWEAK
MMED
MSTRO
8
EBREAK
+
17
18
-
7
DBODY
LSOURCE
SOURCE
3
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = -7.5e-7
res.rdrain n50 n16 = 22.5e-3, tc1 = 8.5e-3, tc2 = 1.2e-5
res.rgate n9 n20 = 2.2
S1A
12 13
8
S2A
14
15
13
res.rldrain n2 n5 = 10
S1B
S2B
res.rlgate n1 n9 = 13.4
res.rlsource n3 n7 = 5.9
CA
13
CB
+
+ 14
res.rslc1 n5 n51= 1e-6, tc1 = 3e-2, tc2 =5.3e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 15.3e-3, tc1 = 1e-3, tc2 =1e-6
EGS
6
8
-
EDS
5
8
-
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 2e-7
res.rvthres n22 n8 = 1, tc1 = -1.4e-3, tc2 = -7e-6
RBREAK
17
18
RVTEMP
19
IT
-
VBAT
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 67.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5))
}
}
©2003 Fairchild Semiconductor Corporation
Rev. B
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