HY57V56820CLT 查看數據表（PDF） - Hynix Semiconductor

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HY57V56820CLT

4 Banks x 8M x 8Bit Synchronous DRAM

Hynix Semiconductor 

HY57V56820C(L)T

CAPACITANCE (TA=25°C, f=1MHz)

Parameter

Pin

Symbol

Input capacitance

CLK

CI1

A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS,

CI2

WE, UDQM, LDQM

Data input / output capacitance DQ0 ~ DQ15

CI/O

-6/K/H

Min

Max

2.5

3.5

2.5

3.8

4.0

6.5

OUTPUT LOAD CIRCUIT

-8/P/S

Unit

Min

Max

2.5

4.0

pF

2.5

5.0

pF

4.0

6.5

pF

Output

Vtt=1.4V

RT=250 Ω

Output

50pF

50pF

DC Output Load Circuit

AC Output Load Circuit

DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)

Parameter

Symbol

Min.

Max

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

ILO

VOH

VOL

-1

1

-1

1

2.4

-

-

0.4

Note :

1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V

2.DOUT is disabled, VOUT=0 to 3.6V

Unit

uA

uA

V

V

Note

1

2

IOH = -4mA

IOL = +4mA

Rev. 0.4 / July 2003

5

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