ADSP-21MSP58BST-104 查看數據表（PDF） - Analog Devices

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ADSP-21MSP58BST-104

DSP Microcomputers

Analog Devices 

ADSP-21msp58/59

seven wait states are automatically generated. This allows, for

example, a 38 ns ADSP-21msp58/59 to use a 250 ns EPROM

as external boot memory. Multiple programs can be selected

and loaded from the EPROM with no additional hardware. The

on-chip program memory can also be initialized through the

HIP.

The ADSP-21msp58/59 features a general purpose flag output

whose state is controlled through software. You can use this

output to signal an event to an external device. In addition, the

data input and output pins on SPORT1 can be alternatively

configured as an input and an output flag.

A programmable interval timer can generate periodic interrupts.

A 16-bit count register (TCOUNT) is decremented every n

cycles, where n–1 is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

The ADSP-21msp58/59 instruction set provides flexible data

moves and multifunction (one or two data moves with a compu-

tation) instructions. Every instruction can be executed in a

single processor cycle. The ADSP-21msp58/59 uses an alge-

braic syntax for ease of coding and readability. A comprehensive

set of development tools supports program development.

Serial Ports

The ADSP-21msp58/59 processors include two synchronous se-

rial ports (SPORT0 and SPORT1) for serial communications

and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-21msp58/59

SPORTs. Refer to the ADSP-2100 Family User’s Manual for fur-

ther details.

• SPORTs are bidirectional with a separate, double-buffered

transmit and receive section.

• SPORTs can use an external serial clock or generate their own

clock internally.

• SPORTs have independent framing for the transmit and

receive sections. Sections run in a frameless mode or with

frame synchronization signals internally or externally gener-

ated. Frame sync signals are programmed to be active high or

low, with either of two pulse widths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

• SPORTs receive and transmit sections generate separate

interrupts when the SPORTs are ready to read or write new

data.

• SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word (Autobuffering

Mode). An interrupt is generated after a complete data buffer

transfer.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24- or 32-word, time-division multiplexed

serial bit stream.

• SPORT1 can be reconfigured as two external interrupt inputs

(IRQ0 and IRQ1) and the Flag In and Flag Out signals (FI,

FO). The internally generated serial clock may still be used in

this configuration.

Pin Descriptions

The ADSP-21msp58 and ADSP-21msp59 are available in a

100-lead TQFP package. Table I contains the pin descriptions.

Table I. ADSP-21msp58/59 Pin List

Pin

Group

Name

#

of Input/

Pins Output Function

Digital Pins

Address

14 O

Data

24 I/O

RESET

IRQ2

BR

BG

PMS

DMS

BMS

RD

WR

MMAP

CLKIN,

XTAL

1I

1I

1I

1O

1O

1O

1O

1O

1O

1I

2I

CLKOUT 1 O

HACK

1O

HSEL

1I

BMODE 1 I

HMD0

1I

HMD1

1I

HRD/HRW 1 I

HWR/HDS 1 I

HD7–0/

HAD7–0

8 I/O

HA2/ALE 1 I

HA1–0/

(unused)

SPORT0

2I

5 I/O

SPORT1 5 I/O

or

Address output for program,

data and boot memory spaces

Data I/O pins for program

and data memories. Input

only for boot memory space,

with two MSBs used as boot

space addresses.

Processor reset input

External interrupt request #2

External bus request input

External bus grant output

External program memory select

External data memory select

Boot memory select

External memory read enable

External memory write enable

Memory map select

External clock or quartz crystal

input

Processor clock output

HIP acknowledge output

HIP select input

Boot mode select (0 = Standard

EPROM Booting, 1 = HIP

Booting)

Bus strobe select (0 = RD/WR,

1 = RW/DS)

HIP address/data mode select

(0 = Separate, 1 = Multiplexed)

HIP read strobe or read/write

select

HIP write strobe or host data

strobe select

HIP data or HIP data and

address

Host address 2 or address latch

enable

Host address 1 and 0 inputs

Serial port 0 pins (TFS0, RFS0,

DT0, DR0, SCLK0)

Serial port 1 pins (TFS1, RFS1,

DT1, DR1, SCLK1)

REV. 0

–3–

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