IS62LV12816L-55B 查看數據表（PDF） - Integrated Circuit Solution Inc
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IS62LV12816L-55B
Integrated Circuit Solution Inc
IS62LV12816L-55B Datasheet PDF : 10 Pages
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IS62LV12816L
IS62LV12816LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter
-55
-70
-100
Min. Max.
Min. Max.
Min. Max
Unit
tWC Write Cycle Time
55
70
100
ns
tSCE CE to Write End
50
65
80
ns
tAW Address Setup Time to Write End
50
65
80
ns
tHA Address Hold from Write End
0
0
0
ns
tSA Address Setup Time
0
0
0
ns
tPWB LB, UB Valid to End of Write
45
60
80
ns
tPWE WE Pulse Width
45
60
80
ns
tSD Data Setup to Write End
25
30
40
ns
tHD Data Hold from Write End
0
0
0
ns
tHZWE ! WE LOW to High-Z Output
30
30
40
ns
tLZWE ! WE HIGH to Low-Z Output
5
5
5
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS, Controlled, OE = HIGH or LOW)
ADDRESS
CS
WE
UB, LB
DOUT
DIN
t WC
VALID ADDRESS
t SA
t SCS
t HA
t AW
t PWE1
t PWE2
t PWB
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS) [ (LB) = (UB) ] (WE).
Integrated Circuit Solution Inc.
7
SR020-0C
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