MLX90719 查看數據表（PDF） - Melexis Microelectronic Systems

零件编号

产品描述 (功能)

比赛名单

MLX90719

General purpose timer

Melexis Microelectronic Systems  

MLX90719

General purpose timer

Sleep manager and watch dog

At power-on-reset the MLX90719 is in low power mode (PWD = 1).

When VDD3 reaches 65V (APORH = 1) PWD is reset and the main oscillator starts. To ensure a correct start of

the analog blocks, the CPU is kept in reset status for 215 main clock pulses (typically 8.2ms).

Once the microcontroller is working a watchdog circuitry will generate a system reset if the user program fails to

reset the watchdog counter. The watchdog delay is given by:

Twd = 57344 x 1/Fckm (= 14ms if Fckm = 4MHz)

The watchdog counter is reset each time a 1 is written on bit RSTWD of P7.

To distinguish a wake-up after power-on reset and a wake-up after low power mode, one can read the status of

bit FLAG (read/write bit in P7). This will be 0 after power on reset and 1 after low power mode if FLAG has been

set during normal mode.

The low power mode is set by bit PWD of P7. Since the main oscillator stops as soon as PWD = 1, setting bit

PWD must be the last instruction of the supply interrupt subroutine (see interrupt controller).

Debouncing

A debounce circuit eliminates positive spikes on line APORH to avoid unexpected wake-up due to distur-

bances. The debounce time (tdaporh) depends on OXBAT.

If OXBAT = 1 it derives from the crystal oscillator frequency and:

7.8ms < tdaporh < 11.7ms

If OXBAT = 0 it derives from the low power RC oscillator frequency and:

3.2ms < tdaporl < 24ms

Timer

The MLX90719 includes a 17-bit timer preceded by a 15-bit prescaler. The clock of the timer can be taken from

four different sources defined by the bits MUX0 and MUX1 of P2:

MUX1

MUX0 Timer clock source Description

0

0

CK125K

0

1

D2P15

1

0

D2P9

1

1

D2P3

Main clock divided by 32 (typically 125kHz)

/215 prescale output

/29 prescale output

/23 prescale output

The battery and crystal option (OXBAT) defines which clock is connected to the prescaler input:

If OXBAT =1: the crystal oscillator output (CKX) drives the prescaler input

If OXBAT = 0: the low power RC oscillator output (CKL) drives the prescaler input.

Control bits (P2):

EN24H = 1 enables the 24h mode (see below).

COUNT = 1 enables the counter

TRST = 1 resets the counter and the prescaler.

Normal operation

In normal mode the timer is used as a free-running counter on CK125K. It can be read at any time without stop.

An interrupt is generated when the value of the timer reaches the value of the timer compare written in P1-P0.

Low power mode if crystal oscillator (OXBAT = 1)

In this mode the clock of the timer must be connected to the /215 output of the prescaler (1Hz).

Setting the 24h mode turns the timer into a modulo 86400 counter if a correct value has been written in P1-P0.

The timer being automatically reset when T16=1 and T[15:0] = TCP[15:0], this value must be 517Fh to give T

MMLLXX990027xx19NaGmeeneofraSl epnusroprose timer

RePvaYg.Xe 13

22/Aug/98 Rev 1.0 3P0a/gJeul1/030

Share Link: