LP62S1024B-T 查看數據表（PDF） - AMIC Technology

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LP62S1024B-T

128K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

LP62S1024B-T Series

Timing Waveforms (continued)

Read Cycle 4 (1)

Address

OE

CE1

CE2

DOUT

tRC

tAA

tOE

tOLZ5

tCLZ15

tACE1

tACE2

tCLZ25

tOH

tCHZ15

tOHZ5

tCHZ25

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CE1 = VIL and CE2 = VIH.

3. Address valid prior to or coincident with CE1 transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

6. CE2 is high.

7. CE1 is low.

8. Address valid prior to or coincident with CE2 transition high.

Write Cycle 1 (6)

(Write Enable Controlled)

Address

CE1

tWC

tAW

tCW5

(4)

tWR3

CE2

WE

DIN

DOUT

(4)

tAS1

tWP2

tDW

tWHZ

tDH

tOW

(August, 2004, Version 1.2)

8

AMIC Technology, Corp.

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