LP62S16512-I(2002) 查看數據表（PDF） - AMIC Technology
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LP62S16512-I Datasheet PDF : 14 Pages
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LP62S16512-I Series
Preliminary
512K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
n Operating voltage: 2.7V to 3.6V
n Access times: 55/70 ns (max.)
n Current:
Very low power version: Operating: 50mA (max.)
Standby: 20µA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Data retention voltage: 2.0V (min.)
n Available in 48-ball CSP (8×10mm) packages
General Description
The LP62S16512-I is a low operating current 8,388,608-
bit static random access memory organized as 524,288
words by 16 bits and operates on low power voltage from
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
Product Family
Product
Family
LP62S16512
Operating
Temperature
-40°C ~ +85°C
VCC
Range
2.7V~3.6V
Speed
55ns / 70ns
Power Dissipation
Data Retention Standby Operating
(ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.)
0.3µA
0.5µA
4mA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
n CSP (Chip Size Package)
48-pin Top View
Package
Type
48 CSP
1
2
3
4
5
6
A LB OE A0 A1 A2 CS2
B I/O9 HB
A3
A4
CS1 I/O1
C I/O10 I/O11 A5
A6 I/O2 I/O3
D GND I/O12 A17 A7 I/O4 VCC
E VCC I/O13 NC A16 I/O5 GND
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
H A18 A8 A9 A10 A11 NC
PRELIMINARY (March, 2002, Version 0.2)
2
AMIC Technology, Inc.
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