M13S64164A 查看數據表（PDF） - [Elite Semiconductor Memory Technology Inc.
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M13S64164A Datasheet PDF : 49 Pages
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ESMT
AC Operating Test Conditions
Parameter
Input reference voltage for clock (VREF)
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (VIH/VIL)
Input timing measurement reference level
Output timing reference level
M13S64164A
Operation Temperature Condition -40°C~85°C
Value
0.5*VDDQ
1.5
1.0
VREF+0.31/VREF-0.31
VREF
VTT
Unit
V
V
V/ns
V
V
V
AC Timing Parameter & Specifications
(VDD = 2.3V~2.7V, VDDQ=2.3V~2.7V, TA =-40 °C to 85 °C )
Parameter
Symbol
CL2
-5
min
7.5
Clock Period
CL2.5
tCK
6.0
CL3
5.0
Access time from CLK/ CLK
CLK high-level width
CLK low-level width
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each input)
Input setup time (fast slew rate)
Input hold time (fast slew rate)
Input setup time (slow slew rate)
Input hold time (slow slew rate)
Control and Address input pulse width
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Data strobe edge to output data edge
Data-out high-impedance window from
CLK/ CLK
Data-out low-impedance window from
CLK/ CLK
tAC
tCH
tCL
tDQSCK
tDQSS
tDS
tDH
tDIPW
tIS
tIH
tIS
tIH
tIPW
tDQSH
tDQSL
tDSS
tDSH
tDQSQ
tHZ
tLZ
-0.7
0.45
0.45
-0.6
0.75
0.45
0.45
1.75
0.75
0.75
0.8
0.8
2.2
0.4
0.4
0.2
0.2
-
-0.7
-0.7
max
12
12
8
+0.7
0.55
0.55
+0.6
1.25
-
-
-
-
-
-
-
-
0.6
0.6
-
-
0.45
+0.7
+0.7
Elite Semiconductor Memory Technology Inc.
-6
min
max
7.5
12
6.0
12
6.0
10
-0.7
+0.7
0.45
0.55
0.45
0.55
-0.6
+0.6
0.75
1.25
0.45
-
0.45
-
1.75
-
0.75
-
0.75
-
0.8
-
0.8
-
2.2
-
0.4
0.6
0.4
0.6
0.2
-
0.2
-
-
0.45
-0.7
+0.7
Unit
ns
ns
tCK
tCK
ns
tCK
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
ns
ns
-0.7
+0.7
ns
Publication Date : Mar. 2009
Revision : 1.0
6/49
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