SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MODE
REGISTER
SET
MRS
IDLE
REFA
AUTO
REFRESH
CKEL
CLK
SUSPEND
CKEH
ACT
CKEL
POWER
DOWN
CKEH
WRITE
ROW
ACTIVE
READ
CKEL
WRITE
SUSPEND
WRITE
CKEH
WRITEA READA
READ
WRITE
READ
CKEL
READ
SUSPEND
CKEH
WRITEA
CKEL
WRITEA
SUSPEND
WRITEA
CKEH
WRITEA
READA
PRE
PRE
PRE
READA
CKEL
READA
READA
SUSPEND
CKEH
POWER
APPLIED
POWER
ON
PRE
PRE
CHARGE
MITSUBISHI ELECTRIC
Automatic Sequence
Command Sequence
11