M62429 查看數據表（PDF） - Renesas Electronics

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M62429

SERIAL DATA CONTROL DUAL ELECTRONIC VOLUME

Renesas Electronics 

M62429P/FP

Relationship between Data and Clock

CLOCK

D0

D1

D2

D3

DATA

D8

D9

D10

Reads data signal at the rising edge of clock signal

Latch signal "H"

Reads latch signal at the falling edge of clock

DC Characteristics of Digital Block

Item

"L" level input voltage

"H" level input voltage

"L" level input current

"H" level input current

Symbol

VIL

VIH

IIL

IIH

Min

0

0.8 VCC

–10

—

Limits

Typ

~

~

—

—

AC Characteristics of Digital Block

Item

Symbol

Min

Cycle time of clock

tcr

4

Pulse width of clock ("H" level)

tWHC

1.6

Pulse width of clock ("L" level)

tWLC

1.6

Clock rising time

tr

—

Clock falling time

tf

—

Data setup time

tSD

0.8

Data hold time

tHD

0.8

Max

0.2 VCC

VCC

10

10

Unit

Test Conditions

V Data, clock pin

V

µA VI = 0

Data, clock pin

µA VI = 5 V

Limits

Typ

Max

Unit

—

—

µs

—

—

µs

—

—

µs

—

0.4

µs

—

0.4

µs

—

—

µs

—

—

µs

Clock and Data Timing

CLOCK

75%

25%

tr

DATA

tWHC

tcr

tf

tWLC

tSD

tHD

REJ03F0209-0300 Rev.3.00 Jun 15, 2007

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