MK2731-03C 查看數據表（PDF） - Integrated Circuit Systems

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MK2731-03C

MPEG Audio Clock Synthesizer

Integrated Circuit Systems 

MK2731-03C

MPEG Audio Clock Synthesizer

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

Inputs and Clock Outputs

Referenced to GND

Ambient Operating Temperature

Soldering Temperature

Max of 10 seconds

Storage temperature

DC CHARACTERISTICS (VDD = 5.0V unless noted)

Operating Voltage, VDD

Input High Voltage, VIH, X1 pin only

Input Low Voltage, VIL, X1 pin only

Input High Voltage, VIH

Input Low Voltage, VIL

Output High Voltage, VOH

IOH=-25mA

Output Low Voltage, VOL

IOL=25mA

Output High Voltage, VOH, CMOS level

IOH=-8mA

Operating Supply Current, IDD

No Load

Short Circuit Current

Each output

Input Capacitance

S2, S1, S0

Frequency synthesis error

All clocks

AC CHARACTERISTICS (VDD = 5.0V unless noted)

Input Crystal or Clock Frequency

Input Crystal Accuracy

Output Clock Rise Time

0.8 to 2.0V

Output Clock Fall Time

2.0 to 0.8V

Output Clock Duty Cycle

At 1.4V

Maximum Absolute Jitter, short term

Minimum Typical Maximum Units

7

V

-0.5

VDD+0.5 V

0

70

°C

260

°C

-65

150

°C

3.13

5.50

V

(VDD/2)+1 VDD/2

V

VDD/2 (VDD/2)-1 V

2

V

0.8

V

2.4

V

0.4

V

VDD-0.4

V

25

mA

±100

mA

7

pF

0

ppm

27.00

±30

1.5

1.5

40

60

see table on following page

MHz

ppm

ns

ns

%

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

External Components

The MK2731-03 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.1µF should be connected between VDD and GND on pins 3 and 5, as close to the

MK2731-03 as possible. A series termination resistor of 33Ω may be used for each clock output. The input

crystal must be connected as close to the chip as possible. The input crystal should be a parallel resonant,

fundamental, AT cut 27 MHz. For accurate tuning of the output when a crystal input is used, capacitors

should be connected between X1 and ground, and X2 and ground. The value of these capacitors is given by

the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-10) x 2. So for a

crystal with 16 pF load capacitance, two 12 pF caps can be used.

MDS 2731-03C D

3

Revision 011101

Integrated Circuit Systems, Inc.• 525 Race Street, San Jose, CA, 95126 • (408) 295-9800 tel • www.icst.com

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