MIL-STD-883 查看數據表（PDF） - Austin Semiconductor

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MIL-STD-883

1 MEG x 4 DRAM Fast Page Mode DRAM

Austin Semiconductor 

Austin Semiconductor, Inc.

DRAM

MT4C4001J

GENERAL DESCRIPTION (cont.)

cycle is always initiated with a row address strobe-in by RAS\

followed by a column address strobed-in by CAS\. CAS\ may

be toggled-in by holding RAS\ LOW and strobing-in different

column addresses, thus executing faster memory cycles.

Returning RAS\ HIGH terminates the FAST PAGE MODE

operation.

Returning RAS\ and CAS\ HIGH terminates a memory cycle

and decreases chip current to a reduced standby level. Also,

the chip is preconditioned for the next cycle during the RAS\

HIGH time. Memory cell data is retained in its corrected

stated by maintaining power and executing any RAS\ cycle

(READ, WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or

HIDDEN REFRESH) so that all 1,024 combinations of RAS\

addresses (A0-A9) are executed at least every 16ms,

regardless of sequence. The CBR REFRESH cycle will

invoke the internal refresh counter for automatic RAS\

addressing.

FUNCTIONAL BLOCK DIAGRAM

FAST PAGE MODE

WE\

CAS\

*EARLY-WRITE

DETECTION CIRCUIT

NO. 2 CLOCK

GENERATOR

DATA IN

4

BUFFER

DATA OUT

BUFFER

4

4

DQ1

DQ2

DQ3

DQ4

OE\

COLUMN

10

ADDRESS

A0

BUFFER

A1

A2

A3

REFRESH

CONTROLLER

A4

A5

A6

A7

A8

REFRESH

COUNTER

A9

10

10

ROW ADDRESS

BUFFERS (10)

10

10

COLUMN

DECODER

4

1024

SENSE AMPLIFIERS

I/O GATING

1024 x 4

Vcc

Vss

MEMORY

1024

ARRAY

RAS\

NO. 1 CLOCK

GENERATOR

NOTE: WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE)

CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE)

MT4C4001J

Rev. 2.2 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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