MX66C256MI-10 查看數據表（PDF） - Macronix International

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MX66C256MI-10

Very Low Power 32k x 8 CMOS SRAM

Macronix International 

WRITE CYCLE2 (1,6)

ADDRESS

CE

WE

D OUT

D IN

MX66C256

t WC

(11)

t CW

(5)

t AW

t WP

(2)

t AS

(4,10)

t WHZ

t DH

(7)

(8)

t DW

t DH

(8)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE active

and WE low. All signals must be active to initiate a write and any one signal can terminate

a write by going inactive. The data input setup and hold timing should be referenced to the

second transition edge of the signal that terminates the write.

3. TWR is measured from the earlier of CE or WE going high at the end of

write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite

phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the

WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = VIL ).

7. DOUT is the same phase of write data of this write cycle.

8. DOUT is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals

of opposite phase to the outputs must not be applied to them.

10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1b.

The parameter is guaranteed but not 100% tested.

11. TCW is measured from the later of CE going low to the end of write.

P/N DS0035

7

Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131

Tel (408)453-8088 Fax (408)451-0876 www.macronix.com

Rev. 1.1, Jan., 2000

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