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C165 查看數據表(PDF) - Siemens AG

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C165 Datasheet PDF : 49 Pages
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C165
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
PORT0:
P0L.0 – 43 –
P0L.7, 50
P0H.0 - 53 –
P0H.7 60
PORT1:
P1L.0 –
P1L.7,
P1H.0 -
P1H.7
61 -
68
69 - 70,
73 - 78
RSTIN 81
RSTOUT 82
NMI
83
Input (I) Function
Output (O)
I/O
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed bus
modes and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width: 8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 - D7
P0H.0 – P0H.7:
I/O
D8 - D15
Multiplexed bus modes:
Data Path Width: 8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7
AD0 - AD7
P0H.0 – P0H.7:
A8 - A15
AD8 - AD15
I/O
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed
bus mode.
I
Reset Input with Schmitt-Trigger characteristics. A low level at
this pin for a specified duration while the oscillator is running
resets the C165. An internal pullup resistor permits power-on
reset using only a capacitor connected to VSS.
O
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C165 to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Semiconductor Group
7

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